A simple NAND Flash Cell diagram is shown above. The NAND flash cell is made from a floating gate transistor. Electrical charge is stored on the floating gate which is isolated above and below by oxide insulating layers.
In its simplest form when the floating gate is charged, it is programmed and recognized as a binary 0. When the floating gate has no charge it is erased and recognized as a binary value of 1.
| FLOATING GATE STATE | REFERRED TO AS | BINARY VALUE ASSIGNED |
| CHARGED | PROGRAMMED | ZERO – 0 |
| NO CHARGE | ERASED | ONE – 1 |
The floating gate remains in its charged or uncharged state until it is changed by surrounding circuitry. Removing power from the NAND device does not affect the state of the floating gate which is why it is such a valuable device for data storage.
How to Read a NAND Cell:
To read a cell, voltage is applied to the control gate and current flow from the source to drain is attempted.
If there is no current flow, it signifies the floating gate is charged (binary 0) – as in the diagram above. If there is current flow, the floating gate is not charged (binary 1) – as in the diagram below.
How to Write a NAND Cell:
To write a cell, a high voltage is applied to the control gate and electrons move from the silicon substrate to the floating gate. This process is called tunneling since the electrons “tunnel” through the oxide insulator to reach the floating gate. See diagram below.
How to Erase a NAND Cell:
To erase a NAND cell, a high voltage is applied to the silicon substrate and electrons move from the floating gate to the silicon substrate. This uses the same tunneling process as the writing process. See diagram below.
NAND Cell life:
The tunneling process described in the Write and Erase functions above cause stress on the oxide insulator layer. Over time this stress breaks down the oxide layer and the floating gate becomes unable to maintain a charge. At some point the cell is no longer usable and must be retired. This is what is responsible for the finite number of writes/erases per cell of NAND flash.
